1. Field of the Invention
This invention relates to an electronic system and, more particularly, to the distribution of a clock signal among multiple subsystems of the electronic system with minimal differential (i.e., "skew") among times in which the clock transitions arrive at select subsystems.
2. Description of the Related Art
An electronic system, such as a computer or microprocessor encompasses numerous subsystems necessary to carry out its intended function. A subsystem which utilizes a clock signal is defined as any component (active or passive) which triggers from the clock signal, or may include multiple components coupled together in sequential fashion. Interconnected transistor and resistor components include, for example, a flip-flop, latch, register, etc. A subsystem may be sufficiently large and contain multiple sequential elements coupled together to carry out a systematic result.
Regardless of the relative size of a subsystem, it is important that a sequential subsystem be clocked or modulated by a clocking signal. Thus, the subsystem requires a clocking signal input to the subsystem to control reception and transfer of data also arriving upon the subsystem.
Proper operation of an electronic system requires that system be synchronized with the clocking signal. Thus, the clocking signal should arrive at select subsystems at the same time. Otherwise, reliable data reception and transmission is not ensured. For example, if data is clocked into one subsystem later than data is clocked into another, the earlier-clocked data may contend with and destroy the later-clocked data before that data is properly stored. The problem of data contention and the lack of concurrency by which the clocking signal arrives at each of the synchronized subsystems is often referred to as "clock skew". Increases in clock skew correspondingly increases the amount of time that the data must remain stable on the bus and/or conductor. This, in turn, will increase the time required for each data transfer on the bus and therefore will reduce the speed of the bus. A conventional solution to clock skew involves accounting for differences in arrival time by buffering distally located subsystems. This requires knowing where the subsystems are located relative to one another--either their location within a monolithic silicon substrate or within a printed circuit board (PCB) between monolithic silicon. Knowing which subsystem is to receive a buffered clocking signal also assumes that the designer can forecast an accurate propagation delay from the clocking source to each destination fed by the clocking signal. Knowing the relative location and propagation delay is difficult to accurately model especially since clock skew will vary depending on fabrication processes and operating temperatures.
It would be desirable to seek an electronic system employing a clock generation circuit which can account (i.e., compensate) for varying clock skews while the electronic system is operating. Operating conditions of the electronic system ensures an accurate indication of the actual clock skew. Knowing the actual clock skew and offsetting that clock skew immediately at the clock signal destination would prove advantageous. It would be further beneficial for the improved clock generation circuit to be used at multiple subsystems to account for the dissimilar clock skews among those subsystems. The clock skews can arise from dissimilar resistive and capacitive loads seen across multiple subsystem destinations of a single conductor carrying the clocking signal. Accordingly, the desired electronic system can make the clocking transitions occur more quickly in greater skew subsystems and yet make the clocking transitions occur less quickly in lesser skew subsystems, each of which are coupled to a single conductor containing the clocking signal.